IBM (NYSE: IBM) and Siemens have announced a research collaboration to advance IBM's nanostack architecture, a transistor design unveiled earlier this year. The partnership combines IBM's semiconductor device innovation with Siemens' expertise in electronic design automation (EDA), process simulation, lithography optimization, and advanced manufacturing software.
Nanostack is described as the industry's first known three-dimensional, nanosheet-based design. It vertically stacks and staggers transistors to pack more of them onto a chip, with nearly 100 billion transistors in a space the size of a fingernail at its current 7 angstrom node. The design also allows different material combinations within each stacked layer, so each transistor's performance and power efficiency can be optimized independently. IBM says these innovations enable substantial leaps in energy efficiency, performance, and SRAM scaling.
IBM demonstrated the viability of the architecture earlier this year, but further advances are needed before it can be manufactured at scale. Under the collaboration, the companies will work on the design, simulation, and lithography techniques required for this and future nanostack generations beyond the 7 angstrom node. A key part of the work is developing advanced virtual models that allow engineers to measure performance, optimize designs, and address fabrication challenges before chips are built.
Huiming Bu, Vice President of Silicon Technology R&D at IBM, described nanostack as a scalable platform that shifts device scaling from 2D to 3D, a path forward for logic scaling needed to support AI and other emerging technologies over the coming decade. Ankur Gupta, Executive Vice President of Siemens' EDA IC Portfolio, said the companies aim to accelerate development cycles and build the manufacturing foundation needed to bring nanostack toward production.
Source: TechPowerUp News · Summarized by HeadlinesBriefing