According to ET News citing supply chain sources, TSMC is holding back from investing in hybrid bonding technology for HBM memory integration. Hybrid bonding creates a permanent bond between silicon chips using embedded metal bumps fused together, eliminating traditional bumps and directly bonding copper interconnections. While chip solder bumps are ~100 micrometers and microbumps ~20 micrometers, hybrid bonding reduces this to 1 micrometer.

TSMC plans to bypass hybrid bonding for HBM and instead invest in 5-micrometer microbumps, preparing its supply chain with South Korean and Japanese suppliers for mass production in the second half of 2028. This approach contrasts with AMD's 3D V-Cache, which uses hybrid bonding to stack SRAM on logic. TSMC continues to favor established methods, similar to its reliance on Low-NA EUV lithography with multi-patterning for advanced nodes until 1nm and below, despite industry views that hybrid bonding is the most efficient high-performance chip stacking method.