NVIDIA has announced NVHBM, a custom high-bandwidth memory technology that integrates the memory controller into the 3D HBM stack rather than the compute die. This architectural shift frees up to 25% more compute die area and reduces I/O footprint by up to 67% compared to JEDEC HBM4E, simplifying interposer routing and enabling up to 80% more usable silicon across the layout.

NVIDIA claims NVHBM delivers up to 30% higher memory bandwidth and 15% lower HBM power consumption versus standard HBM4E. The power reduction provides critical thermal headroom for data centers; NVIDIA estimates a 1-gigawatt facility using 2,000 W XPUs could gain capacity for 15,000 additional units.

At Hot Chips 2026, Samsung confirmed HBM4E at 16 Gbps per pin, reaching 4 TB/s per stack. With NVHBM's 30% improvement, a single stack could theoretically hit 5.2 TB/s. NVIDIA will validate NVHBM across multiple memory vendors and announced Amazon's Annapurna Labs as the first confirmed partner collaborating on the technology through NVLink Fusion.