JEDEC released a free update to its LPDDR5/5X Serial Presence Detect specification. The new JESD406-5D standard adds a calculation for recovery time when memory switches between operating modes. This tweak lets designers fine‑tune power‑saving transitions without sacrificing speed.

LPDDR5/5X chips support two timing sets: a full‑speed mode and a reduced‑speed mode that cuts power. The ability to switch between them extends battery life in mobile devices and offers a low‑power option for growing data‑center deployments. Manufacturers can now schedule mode changes more efficiently.

The new standard documents key parameters for calculating the switching time between fast and low‑power modes, making the feature more efficient and allowing higher system performance. Bill Gervasi, chair of the JEDEC SPD Task Group, said the updates help systems optimize performance while keeping a lower power profile.

By standardizing mode‑switch calculations, JEDEC removes a long‑standing source of uncertainty for memory designers. The update streamlines power‑management workflows and paves the way for tighter integration of LPDDR5/5X in both mobile and server environments. The change is already in effect, and vendors can adopt it without delay.