JEDEC has published the JESD82-552 DDR5 Multiplexed Rank Data Buffer (MDB) standard, a key update for high-bandwidth memory modules. The new standard defines next-generation data buffer functionality for DDR5 MRDIMM architectures, supporting robust operation as module bandwidth scales. This builds on JEDEC's ongoing work with multiplexed rank DIMM designs for enterprise and AI applications.

Progress continues on the JESD82-542 Multiplexed Rank Registering Clock Driver (MRCD) standard, expected soon. The JC-45 Committee is nearing completion of MRDIMM Gen 2, targeting higher bandwidth and system efficiency. These advancements aim to meet growing data demands from AI, cloud computing, and enterprise workloads.

JEDEC is also developing Gen 2 raw card designs targeting 12,800 MT/s and working on MRDIMM Gen 3 standards. The coordinated efforts reflect JEDEC's role in aligning industry standards for interoperable, high-performance memory solutions. These updates position DDR5 MRDIMM as critical infrastructure for next-generation computing platforms.