AMD has unveiled its 6th Gen EPYC server processors, codenamed "Venice," featuring the "Zen 6" microarchitecture. The "Venice" family comprises four product lines: EPYC 9006 (Socket SP7) for mainline servers, EPYC 9006 (Socket SP8) for enterprises, EPYC 9006X SP7 for high-performance computing (HPC), and EPYC 9006 LP "Verano" for AI host nodes.

The processors offer core counts up to 96-core/192-thread with "Zen 6" cores, and up to 256-core/512-thread with "Zen 6c" cores. HPC variants boast up to 1,152 MB of L3 cache per socket. The memory subsystem is enhanced with a 16-channel DDR5 interface supporting DDR5-8000 RDIMMs, and some variants include 24-channel LPDDR5X interfaces. The platform supports 1P and 2P configurations, with 128 PCI-Express Gen 6 lanes per socket and CXL 3.1 support.

AMD highlights significant performance gains over competitors like Intel and Arm, citing up to 18x the throughput compared to its 1st Gen EPYC processors. Specific claims include up to 2.2x the throughput against NVIDIA Vera and up to 1.3x higher per-core performance against Intel Xeon 6980 P. The "Venice" series is currently in production, with staggered releases throughout 2026 and 2027.