At the 2026 IEEE/JSAP VLSI symposium, imec unveiled a 300 mm integration route for 2D‑material transistors developed with ASML and TSMC. The collaboration produced n‑type MoS₂ FETs and p‑type WS₂ or WSe₂ devices on a 50 nm contacted‑poly pitch, the first wafer‑scale demonstration at that metric. Measured I‑V curves confirmed stable operation for both device types.

Fabrication relied on single‑patterning EUV lithography, depositing the TMD layer onto pre‑etched tungsten trenches that serve as bottom contacts. This reverse thin‑film transistor flow produced near‑zero off‑current at Vg = 0 V and yielded 94 % functional transistors with an Imax/Imin ratio above 10⁵. WSe₂ p‑FETs approached the performance of the best laboratory prototypes.

The process accommodates other 2D channels beyond MoS₂, WS₂ and WSe₂, suggesting a versatile platform for future material exploration. By integrating both n and p devices on the same 300 mm wafer, the approach mimics conventional CMOS layouts while retaining the electrostatic control advantages of atomically thin channels. This compatibility reduces the barrier for fab adoption.

Executives from TSMC and ASML stressed that the breakthrough de‑risks the lab‑to‑fab transition and aligns 2D transistor scaling with the most advanced EUV nodes, which can reach 28 nm gate lengths. If the industry adopts this flow, 2D transistors could supplement silicon in ultra‑scaled logic, back‑end and wafer‑backside applications, expanding the roadmap.