CEA-Leti unveiled a significant advancement in 3D integration technology at ECTC 2026, demonstrating functional die-to-wafer hybrid bonding with pitches as small as 1 μm. This breakthrough targets high-performance computing, smart vision systems, and artificial intelligence applications where traditional scaling approaches face fundamental physical barriers.

The French research institute successfully tested structures containing up to 100,000 interconnect links, confirming electrical performance and yields from 5 μm down to 2 μm pitch. However, achieving the 1 μm target required overcoming substantial alignment accuracy challenges, with current bonding tools limiting yield at that scale. Chemical mechanical planarization optimization proved essential for the wafer reconstruction process.

Looking ahead, CEA-Leti plans to integrate this D2W technology with high-density through-silicon vias and through-oxide vias to enable multi-die stacking architectures. A second-generation test vehicle targeting 0.5 μm pitch will further push interconnect density for next-generation AI accelerators, addressing escalating bandwidth demands that conventional approaches cannot satisfy.

This work, supported by the FAMES Pilot Line and ANR NextGen project, builds on over 15 years of hybrid bonding research. The technology combination of D2W and wafer-to-wafer approaches offers both performance and cost advantages for future digital systems, potentially reshaping semiconductor design as Moore's Law slows.