Fraunhofer IPMS researchers demonstrated a wafer‑level method that embeds tiny chiplets into silicon pockets, creating a single‑unit system. The technique, part of the European APECS pilot line, fuses control electronics, sensors and MEMS without traditional packaging steps. By leveling the surface with a passivation layer, the team achieved the first milestone on the quasi‑monolithic integration roadmap for future devices.

The approach promises higher performance by shortening signal paths, which cuts loss and latency, and improves reliability by eliminating mechanical interfaces. Because interconnects form during front‑end‑of‑line processing, connection density surpasses that of conventional packaging. These gains translate into compact, cost‑effective solutions suited for AI accelerators and high‑bandwidth transceivers, where space and speed are critical and lower power consumption.

Dr. Lukas Lorenz notes the current demo uses dummy structures, but the full process chain can migrate to real‑world components, opening a scalable path for heterogeneous systems. Fraunhofer IPMS now seeks industrial partners to apply the method, aiming to shrink development cycles and boost production yields. The breakthrough positions Europe across automotive, aerospace and telecom sectors to compete in next‑gen chiplet ecosystems.