NanoIC, the European pilot line coordinated by imec, has released two advanced interconnect process design kits that enable high-density chip-to-chip connectivity. The fine-pitch redistribution layer (RDL) and die-to-wafer (D2W) hybrid bonding PDKs provide early-access design tools for universities, startups, and industry innovators working on next-generation semiconductor technologies.

These PDKs address a critical bottleneck in advanced packaging, where performance and energy efficiency depend on how effectively multiple chiplets can communicate. The fine-pitch RDL PDK achieves line widths and spaces down to 1.3 microns with microbump pitches as tight as 20 microns, enabling up to 40% faster communication and 15% lower energy per bit on UCIe-Advanced interfaces. The D2W hybrid bonding PDK creates ultra-dense 3D connections through direct oxide-to-oxide links, eliminating the parasitics of traditional copper bumping.

This release marks imec as the first organization to offer easy-access interconnect PDKs at these integration levels. The initial 'exploratory version' provides essential design tools including layout creation, automated routing, and design rule checks. According to Nicolas Pantano, head of the demonstrator architect team at imec, these PDKs will evolve from pathfinding tools into complete fabrication-ready kits with tape-out capabilities, allowing designers to validate concepts in silicon rather than just simulation.