Samsung presented its updated memory roadmap at SEMICON Taiwan 2026, with HBM5 and zHBM as the main focus. HBM5 aims for 2x performance, 20% higher efficiency per watt, and 20% lower thermal resistance using a 2 nm base die and 12-20 layer stacks, targeting mass production in 2028. zHBM stacks memory directly on the processor, targeting 8x raw performance and 3x efficiency per watt with 75-90% lower thermal resistance; concept models unveiled at FMS 2026 with launch expected after 2029. Samsung also confirmed shipping HBM4E at 16 Gbps per pin and current HBM4 at 11.7 Gbps per pin.

On NAND, Samsung develops z NAND-O targeting 10x bit density and 7x read bandwidth with 2028 sampling. The industry is rethinking HBM architecture, with NVIDIA also advancing NVHBM by moving the memory controller into the HBM base die.