According to ET News citing supply chain sources, TSMC is reportedly holding back from investing in silicon packaging technology known as hybrid bonding. The technology creates a permanent bond between silicon chips using embedded metal bumps fused together to form a single chip. In modern packaging, microbumps are approximately 20 micrometers, while hybrid bonding reduces this size to 1 micrometer.

For TSMC, the future may involve bypassing hybrid bonding and investing in 5-micrometer microbumps to enhance performance. South Korean and Japanese suppliers are reportedly collaborating with TSMC to achieve this, with mass production of 5-micrometer microbumps expected in the second half of 2028. As a reminder, AMD's 3D V-Cache technology uses hybrid bonding to put SRAM on top of logic, but TSMC only has limited production capacity of that for now.

This isn't the first instance where TSMC has opted not to adopt the latest packaging technology; the company still believes Low-NA EUV lithography will suffice for advancing next-generation nodes until manufacturing begins for nodes at 1 nanometer and below. This trend continues with microbumps, even as the entire industry, including SK hynix, views hybrid bonding as the most efficient method for stacking chips.