中国内存制造商 CXMT reportedly struggling with HBM3E production, achieving only a 25% yield. Three out of four HBM3E stacks are defective, attributed to immature through-silicon via (TSV) technology. Front-end manufacturing yields around 30%, with back-end processing adding roughly 70% on top of that baseline.

CXMT is attempting HBM3E with approximately 3,000 TSVs per layer across an 8-Hi configuration, compared to Samsung's roughly 5,000 TSVs per layer on HBM2 and SK hynix's over 8,000 on HBM3. The company is unlikely to move to a 12-Hi HBM in the near term as it addresses these engineering hurdles.

Despite the setbacks, analysts note it is too early to write off CXMT. Samsung improved HBM4 yields from about 60% in February to roughly 80% just six months later. CXMT already reaches 90% yield on planar DRAM, only 2-3% behind Samsung's DDR5 output at the 10 nm class node, suggesting a path to catch up with time and refinement.