Synopsys, Inc. today announced breakthroughs in its hardware-assisted verification (HAV) portfolio, introducing software-defined platforms to address escalating AI chip verification demands. These advancements aim to accelerate validation for complex multi-die and AI chips, critical as large language models double in size every four months and edge AI architectures demand ultra-low latency and power efficiency. The company’s solutions now support quadrillions of verification cycles, ensuring first-time-right silicon for data center, edge, and heterogeneous AI systems.

New HAPS-200 and ZeBu-200 platforms leverage AMD’s Versal Premium VP1902 adaptive SoCs, offering 2x higher capacity than prior 6-FPGA systems. These systems enable faster prototyping and emulation for AI workloads, including GPU acceleration, custom accelerators, and networking IPUs. Synopsys also launched the HAPS-200 1 FPGA platform, a desktop solution for IP verification and software bring-up using Interface Prototyping Kits. Collaborations with NVIDIA and AMD highlight the platforms’ role in validating complex AI stacks, with AMD’s Alex Starr emphasizing their value in verifying CPUs, GPUs, and AI subsystems via Real-Number Models.

Industry leaders praise the innovation: NVIDIA’s Narendra Konda noted Synopsys’ software-defined HAV “accelerates system-level verification,” while AMD’s Salil Raje called hardware-assisted verification “critical to meeting time-to-market goals.” The platforms also introduce fault emulation capabilities for safety-critical designs and Real-Number Models for analog behavior abstraction, broadening verification coverage. Continuous software updates ensure scalability for evolving AI workloads.

Availability includes immediate access to the HAPS-200 1 FPGA system, with 12-FPGA versions rolling out in Q3 2026. These tools aim to future-proof verification workflows as AI designs grow in complexity, positioning Synopsys as a key enabler of next-gen AI infrastructure.