Samsung has reworked the power delivery network in its HBM4E memory to address growing engineering challenges in next‑generation AI chips. Two weeks after shipping its first commercial HBM4, the company pushed a steady 11.7 Gbps, with headroom up to 13 Gbps. The new design tackles higher power density in a tighter layout.

Moving from HBM4 to HBM4E adds 775 more power bumps, raising the count from 13,682 to 14,457 while keeping the same die area. Thinner, denser wiring pushes current density and resistance higher, causing IR drop—voltage sagging as it travels—and heat that feeds back into the loop, threatening performance and reliability.

Samsung sliced the large MET4 power block into four smaller sections and further subdivided upper layers to cut congestion and shorten routing paths. The change cut metal‑circuit defects by 97% and reduced IR drop by 41%, giving the chip more voltage headroom for higher speeds and improved reliability.

The company also probes physically separating HBM from the GPU, a move that could ease thermal stress. One proposal uses photonic interconnects, optical links that reach terabit‑per‑second speeds—about 1,000 times faster than copper—to bridge distances beyond 5 cm. Such separation could reshape how AI accelerators are packaged.