Intel and SoftBank’s Saimemory unit unveiled HB3DM, a Z‑Angle Memory stack aimed at beating HBM. The design stacks nine dies—one logic layer beneath eight DRAM layers—using hybrid bonding and about 13,700 TSVs per layer. Each die holds roughly 1.125 GB, giving the module a total of 10 GB capacity for next‑gen AI workloads.

Intel claims the stack can push roughly 0.25 Tb/s per mm², translating to about 5.3 TB/s for the 171 mm² die. That more than doubles the ~2 TB/s per stack delivered by HBM4, positioning HB3DM as a bandwidth leader despite its smaller capacity. HBM4 still reaches up to 48 GB per stack, so the trade‑off remains clear in real‑world benchmarks.

The paper will be presented at VLSI 2026, where Intel may reveal whether additional layers will raise capacity. Production partners and the exact fab node stay undisclosed, but Intel’s involvement hints at a possible return to in‑house DRAM manufacturing. Early adopters of AI accelerators hungry for raw throughput could see their memory hierarchy reshaped today.