NEO Semiconductor delivered a proof‑of‑concept for its 3D X‑DRAM memory using standard 3D NAND lines. Test chips recorded read/write latency under <10 ns, data retention over one second at 85 °C, and endurance beyond 10¹⁴ cycles. Bit‑line and word‑line disturbance also exceeded one second at 85 °C. Development involved NYCU IAIS and NIAR‑TSRI.

Funding arrived via a strategic round led by Acer founder Stan Shih, whose backing signals confidence from veteran silicon leaders. The raise also includes several unnamed venture partners, pushing the total to an undisclosed eight‑figure sum for NEO Semiconductor. TechInsights analysts called the results a tangible step beyond conventional DRAM scaling, noting 3D architectures are now essential for AI‑heavy workloads.

With the silicon demo passing extensive electrical and reliability checks, NEO is courting major memory manufacturers for co‑development. CEO Andy Hsu will detail the metrics at the Future of Memory and Storage conference in Santa Clara next week, where the company also secures booth #507. Early talks suggest integration into next‑generation GPUs and accelerator modules, accelerating the shift from planar DRAM.

Industry partners view the validation as a stepping stone toward commercial 3D DRAM arrays, which could lower cost per gigabit and reduce power draw for AI servers. If licensing proceeds, NEO’s approach may reshape memory supply chains by leveraging the mature 3D NAND ecosystem rather than requiring entirely new fabs.