Rambus introduced a new PCIe 7.0 Switch IP that incorporates Time Division Multiplexing, expanding its interconnect portfolio aimed at AI, cloud and HPC workloads. Built to the PCIe 7.0 spec, the switch promises higher bandwidth density and deterministic latency for systems juggling CPUs, GPUs, accelerators and NVMe storage. Designers can now schedule traffic across shared links, improving fabric utilization.

Simon Blake‑Wilson, senior vice president of Silicon IP at Rambus, said the product gives architects a new degree of freedom to scale bandwidth without adding lanes or endpoints. By multiplexing traffic, the IP reduces system complexity while maintaining low latency, a requirement for both large‑scale AI training and latency‑sensitive inference. Jeff Janukowicz added that efficient link usage is essential for cost‑effective AI platforms.

The switch IP slots into Rambus’ broader PCIe 7.0 suite, which already includes controllers, retimers and debug blocks, enabling faster time‑to‑market for ASICs targeting next‑gen data centers. With AI infrastructure demanding ever‑greater throughput, the addition of TDM‑enabled switching offers a tangible path to higher utilization without sacrificing power or reliability. Customers now have a ready‑made solution to meet the scaling pressures of modern compute clusters.