NextSilicon revealed that its Arbel RISC‑V core will ship as a 64‑core (and a 128‑core variant) enterprise processor aimed at AI and HPC workloads, with volume availability slated for 2028. The chip moves from a test‑chip on TSMC’s 5 nm node to a production‑grade part, incorporating feedback from data‑center operators and AI infrastructure architects gathered after the October preview for enterprise servers in the market.

The production design retains Arbel’s 10‑wide issue pipeline, 480‑entry reorder buffer and four 128‑bit vector units, targeting a 3.4 GHz clock to meet data‑center power and density goals. A TAGE branch predictor aims to match the prediction accuracy of leading x86 and Arm server CPUs, while full Linux and RVA23 compliance make it a drop‑in for existing server stacks for heterogeneous workloads.

RISC‑V’s data‑center segment is projected to grow at a 33.1% CAGR through 2034, topping $200 billion, but performance‑critical workloads have lacked a native high‑single‑thread core. Arbel’s emphasis on strong scalar performance and integrated inference vectors positions it as a potential alternative to x86/Arm CPUs for agentic AI and HPC tasks, giving customers an open‑ISA path free from licensing constraints and future‑proofing.