At CES 2026, AMD CEO Dr. Lisa Su unveiled the next-generation EPYC 'Venice' processor, a cornerstone of the 'Helios' AI rack architecture. This enterprise CPU features a radical package redesign crucial for AI workloads. It moves away from traditional layouts, utilizing two centralized 4nm server I/O dies flanked by up to eight 32-core 'Zen 6' CCDs built on an advanced 2nm node.

This 256-core/512-thread behemoth supports 16-channel DDR5 memory, necessitating the split I/O design linked by high-speed fabric. While it remains unclear if these are high-clock 'Zen 6' or density-optimized 'Zen 6c' cores, the chip promises massive I/O expansion. Increased PCIe and CUL lane counts are essential to drive the rack's four MI455X AI GPUs, DPUs, and 800G NICs, positioning Venice as the definitive engine for next-gen data center AI and HPC.