IBM unveiled a new nanostack transistor architecture that it brands as the world’s first sub‑1 nanometer chip technology. The design packs nearly 100 billion transistors onto a fingernail‑sized die, roughly double the density of IBM’s prior generation. By stacking two three‑nanosheet transistors vertically, the chip claims up to 50 percent higher compute performance or 70 percent better energy efficiency for AI workloads for cloud operators and enterprises.

The architecture builds on IBM’s 2‑nanometer nanosheet process introduced in 2021, but replaces traditional planar layouts with a staggered‑channel design that shrinks SRAM cell height by 40 percent. At the 0.7‑nanometer node—dubbed the 7 angstrom node—the stack achieves three 5‑nanometer nanosheets per transistor, separated by 9 nanometers, enabling the claimed density gains across multiple process layers.

IBM presented the nanostack results at the 2025 IEEE VLSI symposium in Kyoto and followed with SRAM scaling data at the 2026 event. While IBM does not fabricate chips itself, it expects partnerships with foundries such as Rapidus or Samsung to bring the technology to market within five to ten years. If realized, the approach could redefine CPU and GPU scaling for data‑center AI across next‑gen accelerator designs.