Qualcomm unveiled its first High Bandwidth Compute (HBC) module, a hybrid memory‑compute stack that replaces traditional HBM. By stacking low‑power DDR (LPDDR) chips in a 3‑D stack linked with through‑silicon vias, the design promises higher throughput while cutting energy use. The compute die sits beneath the memory layers, handling near‑memory tasks that would otherwise burden the main processor.

On Qualcomm’s AI250 accelerator, the HBC Gen 1 prototype reached 133 TB/s of bandwidth, an 18‑fold jump over the LPDDR5X used in the AI200 card. Qualcomm claims the approach delivers 6x the bandwidth‑per‑watt of current HBM‑4 specifications, positioning the stack as a more efficient alternative for data‑intensive AI workloads.

The company plans to ship HBC Gen 1 with the AI250 accelerator in mid‑2027 and has outlined a roadmap toward Gen 2, which should push bandwidth even higher. While Qualcomm has not disclosed which LPDDR generation or foundry will produce the stack, industry observers suspect Samsung Foundry could play a role given its memory and logic capabilities.

By moving compute closer to memory, HBC could reduce latency for neural‑network inference and lower power budgets in edge devices. If the technology scales, data‑center servers might adopt the stack to meet growing AI bandwidth demands without the significant thermal penalties of conventional HBM today.