Aegis introduces a fully open-source FPGA, from silicon to software, challenging traditional proprietary models. Unlike prior efforts that reverse-engineered closed architectures or relied on external tooling, Aegis designs its fabric, toolchain, and silicon fabrication path using open PDKs and services like wafer.space. The Aegis Terra 1 device targets GF180MCU, featuring 2,880 LUT4s, 128 BRAM tiles, and 64 DSP units, with full RTL-to-GDS workflows for tapeout.

Its architecture follows Xilinx-style conventions, using ROHD to generate synthesizable SystemVerilog, with tile configurations for LUT4, BRAM, DSP, and SerDes. The toolchain integrates Yosys, nextpnr, and custom scripts, enabling synthesis, place-and-route, and simulation. Sky130 PDK support expands its foundry compatibility, while Nix-based builds streamline development. This open approach lowers barriers for hardware innovation, enabling transparent, customizable FPGA development.