Jane Street has released a new puzzle challenging participants to reverse engineer a custom-designed ASIC. This puzzle delves deeper into the tech stack than their previous neural network challenge, providing only the chip's layout (GDS file) and sample inputs/outputs. Participants must recover a netlist from the geometric layout, determine the circuit's function, and find a specific string value to solve the puzzle. The layout itself offers hints, with a dedicated section for output generation that can be ignored initially.

To aid participants, a warm-up example of a simple binary adder is provided, demonstrating the mapping from Verilog source to layout. Free and open-source tools like KLayout or Magic VLSI can be used to examine the GDS files. The challenge encourages collaboration but prohibits spoilers until September 4th, 2026. Submissions are open until this date, with interesting writeups and solutions to be featured later.

This ASIC puzzle serves as a prelude to a larger competition where participants will design their own chips, with the best designs potentially being fabricated. The hardware team at Jane Street works on similar complex problems daily, designing FPGAs and ASICs for high-frequency trading systems.