Cadence has announced a new Chiplet Spec-to-Packaged Parts ecosystem designed to accelerate time-to-market for chiplets targeting physical AI, data centers, and high-performance computing (HPC). The ecosystem integrates IP from partners including Arm, Arteris, eMemory, M31 Technology, Silicon Creations, and Trilinear Technologies, with silicon analytics from proteanTecs. To streamline adoption and reduce risk, Cadence is collaborating with Samsung Foundry to build a silicon prototype on the SF5A process.

A key element is the integration of Arm's Zena Compute Subsystem (CSS), enabling Cadence to address demanding edge AI requirements in automotive, robotics, and drone applications. By reducing engineering complexity, this alliance provides a low-risk path to advanced chiplet adoption, paving the way for more efficient, standards-based systems in next-generation computing.