Spacecraft have historically relied on processors that prioritize survivability over performance, accepting trade-offs due to radiation, extreme temperatures, and multi-year missions. That paradigm is changing with NASA's High Performance Spaceflight Computing (HPSC) project, which entered a testing phase at Jet Propulsion Laboratory (JPL) in May 2026.

Built in partnership with Microchip Technology, HPSC combines multi-core computing, high-speed networking, fault tolerance, AI readiness, and security into a single platform. The Microchip PIC64-HPSC delivers over a hundredfold improvement in performance per watt compared to current space-qualified systems, allowing more power for instruments and communications.

This leap enables new exploration methods. Future missions require more onboard autonomy, sophisticated science instruments, and faster decision-making, especially as communication delays lengthen—radio signals take up to 24 minutes one-way to Mars. HPSC allows spacecraft to process information locally, reducing reliance on Earth-based control.

HPSC is a 64-bit multi-core system-on-chip designed for spaceflight, incorporating radiation-hardened engineering and fault-tolerant capabilities. It supports virtualization, AI workloads, PCIe, CXL, Ethernet, and includes an integrated 240-gigabit-per-second TSN switch, serving as both computing engine and networking backbone.