XCENA, a semiconductor company developing memory-centric computing solutions for AI infrastructure, presented the architecture and measured performance of MX1, its computational CXL memory architecture, during the Hot Chips 2026 Memory session. Presented by Harry Kim, Chief Product Officer, the session examined how MX1 combines large-scale memory expansion, SSD-backed capacity, and programmable near-memory computing in a single CXL Type 3 device.

MX1 integrates three architectural capabilities: memory expansion up to 2 TB of DDR5 across four channels via CXL 3.2 over PCIe 6.0, SSD-backed capacity through XCENA Infinite Memory, and near-memory computing with over 1,000 custom RISC-V cores. Integrated vector engines provide approximately 3 TFLOPS of FP32/FP16 dot-product throughput for workloads like vector search and KV-cache scoring.

Measured performance on six representative data-processing kernels showed a single MX1 delivered up to 4.7x higher throughput and 18.7x greater energy efficiency compared to a host CPU processing data over CXL, and up to 2.0x higher throughput and 6.2x greater energy efficiency versus local DDR5.

Developers program MX1 using standard C/C++ or Rust via XCENA's LLVM-based toolchain. The PXL runtime schedules workloads across RISC-V cores, and the XFLARE library integrates with SQL engines and FAISS. XCENA plans mass production by end of 2026, with initial customer revenue targeted for 2027.