Intel detailed the package design of its next-generation Xeon 7 "Diamond Rapids" server processor at HOT CHIPS, designed as a versatile serial processing powerhouse for enterprise-scale agentic AI. The processor offers up to 256 P-cores per socket, cushioned by up to 1.28 TB of last-level cache. Built on Intel’s 18A-P, 3-T, and 3 foundry nodes, the disaggregated MCM consists of two Fabric Hub Tiles (FHTs), four CPU core Base Tiles, and 16 core chiplets, each containing 16 "Panther Cove" P-cores.

Each base tile provides 320 MB of shared L3 cache among 64 cores, enabling LLC pooling. The core chiplets use a 3D crossbar for core-to-core communication and connect to base tiles via Foveros 3D Direct hybrid bonding. Fabric Hub Tiles, built on Intel 3, provide 16 DDR5 memory channels supporting 12,800 MT/s MRDIMMs and 128 PCIe Gen 6 lanes configurable as CXL 3.0 or UPI 3.

The design includes fixed-function accelerators like TDX, SGX, QAT, and DSA, with Panther Cove P-cores supporting AMX, AVX 10.2, FP8, FP16, and BF16.