TSMC announced it will continue using Low-NA EUV lithography tools instead of adopting costly High-NA EUV scanners, a move that could reshape semiconductor manufacturing economics. The company cited $410 million per High-NA machine as a barrier, opting instead for cheaper Low-NA systems paired with multi-patterning techniques to achieve similar performance. This strategy mirrors Intel’s past struggles with its delayed 10nm node, where reliance on older tools initially hindered progress before EUV adoption became unavoidable.

The multi-patterning approach allows TSMC to etch designs using two Low-NA EUV passes, mimicking High-NA efficiency while avoiding upfront capital expenditures. However, this method has limitations, with TSMC planning to integrate High-NA systems only for nodes at 1nm and below. For now, the tactic lets TSMC maintain a competitive edge with lower costs, though Intel has already embraced High-NA for its 14A node, signaling a shift in industry leadership.

TSMC’s deputy Co-COO, Kevin Zhang, emphasized the company’s R&D success in optimizing existing EUV tech while scaling aggressively. The decision contrasts with Intel’s current High-NA adoption, which addresses issues like aggressive etching demands. While TSMC avoids near-term High-NA costs, the article warns that long-term reliance on Low-NA could risk falling behind as nodes shrink.

This strategy highlights a critical trade-off: balancing immediate cost savings against future technological demands. As ASML’s High-NA systems gain traction, TSMC’s path raises questions about whether its current approach will sustain its dominance or force a hasty pivot later.