IBM unveiled the industry's first sub‑1 nanometer chip, built on a 0.7 nm (7 angstrom) node. The new processor packs roughly 100 billion transistors onto a fingernail‑sized die, almost double the density of IBM’s 2 nm chip from 2021. IBM says the design delivers up to 50 % more performance and 70 % better energy efficiency, targeting AI and cloud workloads in server farms and edge devices.

The breakthrough hinges on IBM’s three‑dimensional nanostack architecture, the first nanosheet‑based design that vertically stacks and staggers transistors. This approach lets engineers mix materials layer‑by‑layer, optimizing each transistor’s speed and power draw. Validation showed functional CMOS inverters and a 40 % SRAM scaling gain, proving the concept can support the data bandwidth demanded by next‑gen AI models.

IBM plans to move nanostack production toward volume manufacturing within five years, leveraging a High NA EUV lithography tool soon to arrive at its Albany site. Partners such as Lam Research, Tokyo Electron and SCREEN Semiconductor are already supplying processes for the new node. If the roadmap holds, the sub‑1 nm era could extend silicon scaling for a decade, reshaping expectations for data‑center and edge devices.