IBM claims it has built the world's first sub-1 nanometer chip using its new "nanostack" architecture. The 0.7nm chip packs nearly 100 billion transistors into silicon no larger than a fingernail, doubling the density of its previous 2nm design. This represents a significant leap from the nanosheet technology IBM used to create 2nm chips in 2021.

Each transistor in the nanostack design consists of three nanosheet elements about five nanometers thick, staggered vertically with roughly nine nanometers between them. The company says this configuration delivers either up to 50 percent more performance or 70 percent greater energy efficiency compared to its 2nm node chips. Jay Gambetta, IBM Research's director, believes the architecture enables more powerful computing without proportional energy increases.

IBM estimates five years before nanostack chips reach mass production, though this timeline seems optimistic given partner Rapidus plans to scale 2nm production only by late 2027. The Japanese chipmaker has been working with IBM to commercialize its nanosheet technology.

The breakthrough matters because it extends Moore's Law trajectory, giving chipmakers a pathway to continue shrinking transistors for at least another decade. IBM will share commercialization details later, but the nanostack architecture provides a concrete foundation for next-generation silicon.