Cadence's AI-driven digital and custom reference flows, tools, and solutions are now certified on Intel 18A-P and Intel 14A technologies, based on the latest Intel Foundry process design kits (PDKs). Building on the companies' recent expansion of design IP optimized for Intel 18A and 18A-P and their multi-year DTCO agreement targeting Intel 14A, this certification provides customers with a signoff-ready path to deploy advanced AI, HPC, and mobile SoCs on Intel Foundry's leading-edge nodes.

Cadence has worked closely with Intel Foundry to co-optimize tools, flows, and methodologies that fully leverage innovations including RibbonFET gate-all-around transistors and advanced backside power delivery technologies such as Power Direct. By tightly coupling process capabilities with Cadence's agentic AI-driven EDA portfolio, customers can achieve industry-leading power, performance, and area (PPA) while reducing design risk and time to market.

The certified flows span the full Cadence portfolio of AI-driven implementation, verification, and signoff solutions. As part of the collaboration, Cadence and Intel Foundry have co-developed an advanced packaging reference design flow supporting EMIB and EMIB-T technologies. Silicon validation of IP test chips on Intel 18A using Cadence interface and memory IP demonstrates robust interoperability.

"The next era of AI, HPC, mobile, and advanced systems innovation will be defined by how quickly customers can move from bold architectural ideas to reliable silicon," said Boyd Phelps, SVP and GM of Silicon Solutions Group at Cadence. Cadence will showcase certified flows at DAC.