AMD is finalizing its RDNA 5 architecture, featuring a complete Dual-Issue VALU pipeline for Wave32 that allows vector operations to be processed simultaneously across X and Y ALU lanes. This enhancement expands the range of FMA and other VOP instructions eligible for dual-issue while relaxing register constraints. The new design enables more intensive floating-point work in Wave32 mode, dramatically increasing FP32 compute utilization for gaming applications.

The previous implementation in RDNA 3 supported only a limited subset of VOP instructions, excluded critical FMA variants, and required strict register-bank separation. Many shaders couldn't exploit X/Y pairing, causing measured FP32 throughput to fall well below theoretical peak performance. This limitation particularly impacted modern games that process vertex and pixel shaders primarily using FP32 compute.

With RDNA 5, gaming performance should finally align with theoretical compute capabilities. AMD plans to release the architecture this year alongside next-gen neural rendering, ML-based upscaling, and advanced ray tracing technologies. The FSR Diamond project represents the extreme evolution of these technologies, promising substantial performance improvements for gamers who rely on FP32-intensive applications.