Startup WIOWIZ in India faced a roadblock when its 1.4 million‑gate NPU stalled Verilator after three days, generating a 56 GB VCD trace. Commercial gate‑level emulators charge half a million dollars annually, a price the fledgling team could not afford, prompting them to build their own solution.

They released VHE (Virtual Hardware Emulator), a GPU‑accelerated gate‑level simulator that pipelines Yosys‑generated netlists through a Python parser, DAG levelizer and CUDA kernels. Benchmarks show 100× faster on an 8 K PicoRV32, 27× on a 1.25 M‑gate mor1kx, and 13× on a 1.4 M‑gate GEMMX, while the 6.7 M‑gate WZ‑NPU runs at 3,444 cycles per second, delivering a peak of 23 billion gate‑evaluations per second.

VHE sidesteps Verilator’s single‑threaded bottleneck and massive trace files by dispatching each logic level as a separate CUDA kernel; the 6.7 M‑gate design fits in 54 MB of GPU memory across 447 levels. Upcoming releases aim to add SDF timing, four‑value logic, waveform export and formal‑tool integration.