Many Java developers treat class design casually, adding methods and fields without considering the performance implications of data layout. While algorithmic complexity gets careful attention, hardware-level optimizations often get overlooked. This changes when you examine how modern CPUs actually fetch and cache data.

A typical machine features 64-byte cache lines with L1d cache at ~35 KiB per core holding roughly 560 cache lines. The memory hierarchy progresses through L2 (~2 MiB), L3 (12 MiB shared), and finally DRAM. Each level introduces significant latency penalties—from 1-2 nanoseconds in L1d to 60-100 nanoseconds for main memory access.

The difference between Array of Structs and Struct of Arrays becomes dramatic with larger data structures. When Monster structs grow to 1KiB, the Struct of Arrays approach delivers up to 30x performance improvements by packing cache lines more efficiently. Smaller structs show less dramatic gains since multiple elements fit within a single cache line anyway.

Random access patterns tell a different story. Pointer-chasing benchmarks reveal that working set size determines which cache tier your data occupies. Keeping tight control over total data size becomes essential when access patterns defeat CPU prefetchers, as performance drops significantly once data spills beyond L1d cache.