DRAM read disturbance, encompassing phenomena like Row Hammer and Row Press, is a critical issue where accessing one DRAM row can unintentionally alter bits in other unaccessed rows. These bitflips jeopardize the reliability and security of DRAM-based systems.

While prior research has experimentally characterized these bitflips and proposed mitigations, and other studies have explored their physical underpinnings, a disconnect exists. Existing device-level models often fail to fully explain empirical observations. This work aims to bridge this gap by unifying experimental characterization with device-level modeling.

The research identifies discrepancies between theoretical physical mechanisms and experimental findings concerning bitflip directions, counts, and the minimum aggressor activations needed (ACmin). Through comprehensive TCAD simulations, the study presents a refined understanding of the error mechanisms for Row Hammer and Row Press, identifying key parameters crucial for aligning simulation results with real-chip behavior. The findings offer implications for improving experimental characterization methodologies and designing more effective mitigation techniques for DRAM read disturbance.