A developer built a fully functional scientific calculator in hardware by designing a custom nibble-oriented CPU in Verilog and running it on an FPGA. The project includes a soft CPU core, ALU, I/O interface, and microcode firmware — all assembled and debugged through a Qt-based simulator that runs in a web browser.

The toolchain spans Verilator simulation, Quartus synthesis for Cyclone II boards, and ModelSim waveform debugging. A custom assembler and script compiler generate the microcode. The repo also houses pathfinding research and algorithm verification modules as separate subprojects.

What makes this interesting is the end-to-end stack: Verilog source feeds into Verilator for desktop or WebAssembly simulation, while Quartus handles FPGA deployment. The entire project ships under CC BY-NC-SA 4.0, so anyone can fork and adapt the CPU design for other hardware math applications.