ECC RAM uses Hamming codes to correct single‑bit errors before data reaches the CPU. The most common form requires R redundant bits to cover 2^R‑R‑1 data bits; for 32‑bit data, R=6, and for 64‑bit, R=7. DDR4 buses are 72 bits wide, but the 64‑bit data path leaves an extra bit, often unused. RDIMM (registered DIMM) adds a buffer that allows larger modules and more sticks, at the cost of slightly higher latency. UDIMMs lack this buffer and are usually non‑ECC. Chipkill, a trademarked term by IBM, extends protection to an entire DRAM chip failure; it is present on many Dell and HP servers and requires an even number of DIMMs.

DDR5 introduces on‑die ECC to handle the higher error rate of smaller, faster cells. The specification defines EC4 (36‑bit data per subchannel) and EC8 (40‑bit data), where EC8 permits full Hamming checks on each 32‑bit subchannel. Most DDR5 RDIMMs are EC8, while some UDIMMs are EC4. EC4 variants are problematic because they may not provide the intended protection.

Mozilla reports that 15 % of Firefox crashes stem from RAM hardware faults, underscoring the need for reliable ECC in consumer systems.