Silicon Motion Technology Corp. unveiled the SM2524XT, a PCIe Gen 5 x4 DRAMless SSD controller aimed at AI inference and KV‑Cache workloads. Built on TSMC’s 6 nm process, it supports up to 4,800 MT/s NAND bandwidth, delivering sequential reads as high as 14 GB/s and random throughput reaching 2.5 million IOPS. The controller supports both NVMe 1.4 and upcoming 1.5 specifications, enabling compatibility with a range of SSD designs.

The chip’s four‑core architecture improves random performance by roughly 25 % over the prior generation, trimming latency for fragmented data streams typical of KV‑Cache. Nelson Duann, Silicon Motion’s senior VP of client and automotive storage, said the controller’s power‑efficiency gains—up to 25 % better performance per watt—keep AI PCs responsive even under sustained load. This focus addresses a growing bottleneck as on‑device large language models demand continuous high‑IOPS access. Manufacturers can also forego separate DRAM modules, reducing BOM costs and thermal design complexity for compact AI devices.

Integration of Silicon Motion’s Separated Command Address (SCA) engine, advanced FTL scheduling, and NANDXtend LDPC ECC further reduces latency spikes and sustains throughput during prolonged inference sessions. By delivering stable random I/O without DRAM, the SM2524XT positions itself as a cost‑effective solution for manufacturers building AI‑centric laptops and edge servers, directly easing the storage choke point.