Qualcomm has officially validated its High Bandwidth Compute (HBC) concept, marking a significant leap in AI accelerator memory technology. The first-generation HBC has successfully passed silicon validation in Qualcomm's San Diego lab, demonstrating full read-write capabilities and near-memory computation. Unlike traditional High Bandwidth Memory (HBM), which stacks DDR layers, HBC utilizes low-power LPDDR memory stacked vertically in a 3D configuration with through-silicon vias (TSVs).
This design offers superior energy efficiency, claiming a 6x increase in bandwidth per watt compared to current HBM specifications. By embedding a compute die at the base of the memory stack, Qualcomm aims to reduce data travel distances to just a few microns, drastically improving processing speeds for AI inference. HBC Gen 1 achieved an impressive 133 TB/s of total memory bandwidth on the AI250 accelerator card, representing an 18x increase over the LPDDR5X used in the AI200 card.
Qualcomm plans to integrate HBC across its AI accelerator portfolio, with the first commercial shipments expected in the first half of 2027 alongside the AI250 AI accelerator.
Source: TechPowerUp News · Summarized by HeadlinesBriefing