AMD unveiled its Versal Premium Gen 2 Memory on Package (MoP) adaptive SoCs, integrating up to 32 GB of LPDDR5X directly into the chip package. The design delivers 288 GB/s of bandwidth while reducing board area requirements by up to 60%, eliminating the need for complex board-level memory routing that traditionally slows development cycles.

These chips target demanding applications where space and power budgets are tight: physical AI workloads, networking infrastructure, aerospace, and defense systems. For years, engineers faced tradeoffs between memory bandwidth and practical constraints like power consumption and longevity. Memory on Package removes this compromise, letting designers build the systems they want rather than what memory limitations allow.

The MoP architecture includes CXL 3.1 and PCIe 6.0 hard IP running at 64 Gb/s, plus LPDDR5X support up to 9,000 Mb/s for memory scaling. Security features span PCIe Integrity and Data Encryption plus DDR memory encryption, while industrial-grade operation from -40°C to 110°C suits mission-critical deployments. The 15-plus-year lifecycle support addresses concerns about HBM's shorter refresh cycles.

Sampling begins at the end of 2026 with production shipments slated for mid-2027. AMD emphasizes the pre-validated memory interface reduces simulation and validation overhead, potentially shortening development timelines. Engineers can start with existing Versal Premium Series Gen 2 devices already shipping, leveraging familiar Vivado and Vitis tool workflows for faster adoption.