Intel has updated its Compute Runtime with support for Portable Instruction Set Architecture (PISA), a new virtual ISA and programming model for Intel GPUs. Unlike CPUs with established ISAs like Arm or x86, GPUs use native instruction sets that change across generations, requiring compilers to handle architecture-specific differences. PISA introduces an abstraction layer, providing a common compiler target so code can be written once and finalized for multiple compatible Intel GPU architectures.

This enables workloads compiled to PISA to run across generations without architecture-specific code generation, while leveraging newer hardware capabilities where supported. Compatibility depends on the target architecture and features used. PISA is not Intel's first virtual GPU ISA; the existing v ISA has long served as an intermediate representation.

The model resembles NVIDIA's Parallel Thread Execution (PTX) virtual ISA, which sits between CUDA code and native machine code, enabling close-to-metal programming. Intel lists close-to-the-metal performance, handwritten library support, and inline assembly as PISA goals. Currently at version 0.1, PISA includes documentation on the OpenCL 3.0-based execution model, data types, registers, and memory addressing, signaling continued investment in future GPU efforts.