At the ISCAS keynote in Shanghai, Huawei unveiled a roadmap to 1.4nm-class chips by 2031 and introduced a new semiconductor scaling model. The company argues that Moore's Law, based on geometric shrinkage, is hitting physical and economic limits, prompting a shift to a time‑based framework the firm calls the Tau (τ) Scaling Law and aims to reshape industry roadmaps.

Using the Tau law, Huawei has already mass‑produced 381 chips across diverse sectors, and it underpins a novel LogicFolding architecture. The design continuously compresses signal propagation delay while raising transistor density, applicable to semiconductors, circuits, and systems alike. Huawei’s 2026 Kirin smartphone processors will be the first to ship with LogicFolding, promising a noticeable performance jump for AI accelerators and edge devices.

The 2031 high‑end chips aim for transistor density equivalent to a 1.4nm process, a claim that would put Huawei ahead of most foundries still limited to 3‑nm nodes. By inviting global partners to collaborate, the firm signals that no single entity can overcome the scaling bottlenecks alone. Huawei’s roadmap sets a clear benchmark for the next decade of chip evolution and could influence standards bodies worldwide.