Intel's "Panther Lake" SoC, with a compute tile on the 18A node, has reportedly achieved an 80% yield. The compute die measures ~8.004 x 14.288 mm (114.304 mm²). This indicates low defect rates and high parametric yield, suggesting Intel is overcoming historic parametric yield problems.

A rumored shift in "Nova Lake" production may confirm this: Intel plans to produce 80-90% of its compute tiles in-house, the rest by TSMC. For 18A, defect rates are now around D0=0.1 or D0=0.2.

Intel is on track to finish the year with about 40,000 18A wafers per month, aiming for 60,000 WPM by end of 2027 and 80,000 WPM in 2028, alongside 14A ramp-up. GF Securities analyst Jeff Pu suggests 14A capacity will be ~6,000 WPM by end of 2027, rising to 24,000 WPM in 2028, before any collaboration with Elon Musk's Terafab project, expected to use Intel 14A.