Japanese semiconductor maker Rapidus faces potential delays to its 2 nm node mass production timeline. According to the Japan Times, volume production is likely pushed back by several months due to difficulties with Static Random Access Memory (SRAM) cells. SRAM serves as foundational building blocks for designs operating on one node, and without functional SRAM, normal volume production is impossible.
Beyond SRAM issues, dust and particle control problems in Rapidus cleanrooms are impacting silicon manufacturing. Engineers are actively working to resolve these cleanroom and SRAM cell problems. Despite these reported challenges, Rapidus claims the 2 nm node will arrive on time.
In mid-2025, Rapidus successfully taped out a 2 nm Gate-All-Around (GAA) test chip at the IIM-1 fab. The company plans to enter high-volume production in Japan's fiscal 2027, ending March 2028. Rapidus has completed significant milestones since breaking ground in September 2023, finishing the cleanroom in 2024 and connecting over 200 advanced semiconductor tools by June 2025.
The company differentiates itself by promising hot lots with a 15-day wafer turnaround, unprecedented at a leading-edge node. Achieving a working 2 nm node would be a major milestone if Rapidus can overcome these current challenges.
Source: TechPowerUp News · Summarized by HeadlinesBriefing