AMD showed off its next-generation EPYC "Verano" server CPUs during CEO Dr. Lisa Su opening keynote at the 2026 OCP Global Summit. The new CPU is the first EPYC processor to support LPDDR5X memory via SOCAMM2 modules, a design that mirrors rival NVIDIA's Vera CPU, which already uses SOCAMM2.
The "Verano" processor sits within the EPYC 9006 "LP" family and is built on the same TSMC 2 nm process as the already-launched EPYC "Venice." While "Venice" is the first EPYC processor based on Zen 6 architecture, "Verano" is optimized for AI tasks in agentic AI racks. AMD plans to pair it with its own Instinct MI500 GPUs via xGMI connectivity at up to 112 Gbps. It will run on the new SP8 platform rather than Venice's SP7.
When AMD first described "Verano," it indicated up to 72 cores on a single-socket platform. That figure has now been updated to up to 192 cores. The initial information suggests either a single large chip or a dual 96-core configuration. System360Cheese on X reported that the chip shown featured eight Zen 6 CCDs, two large IO dies and four LPDDR5X memory controllers. The CCDs appear smaller than Venice's Zen 6C design, suggesting standard 12-core Zen 6 dies rather than the denser 32-core Zen 6C variants.
The announcement follows AMD's earlier reveal of the Helion agentic AI rack, an Open Compute Project spec-designed system into which Verano is expected to be integrated. Availability is targeted for 2027.
Source: TechPowerUp News · Summarized by HeadlinesBriefing