TSMC is developing a new packaging method called CoPoS, or Chip-on-Panel-on-Structure. This approach uses a glass material as a temporary carrier that becomes part of a three-layer sandwich structure in the final substrate. This shift in material and architecture aims to lower manufacturing costs while boosting overall chip performance.

Production for this technology is expected to start by the end of 2028. The company intends to target AI and high-performance computing chips specifically. Because these workloads require massive data throughput and efficiency, the glass-based structure provides the necessary physical foundation to handle the demands of next-generation hardware more effectively than current methods.

Nvidia will be the first to implement this technology with its Feynman AI chipset. By integrating CoPoS, TSMC strengthens its grip on the semiconductor market. This move puts pressure on competitors to develop their own alternatives to keep pace with the performance gains and cost reductions provided by this glass substrate architecture.