Dmitry Grinberg's critique of RISC-V, titled 'They Should Have Known Better,' sparked significant debate across Hacker News and Lobsters. While his technical concerns about instruction set architecture hold merit, they reflect a narrow, privileged perspective that overlooks RISC-V's broader impact. A developer writing from Trinidad and Tobago highlights how shipping costs of $60-200 for inexpensive chips fundamentally change the calculus compared to developers in US and Europe with free shipping.

For educators in regions like Nigeria and Bangladesh, the price difference between ten-cent and one-dollar parts determines whether thirty students each get their own chip or share a single demo board. Instruction set elegance becomes secondary when hardware accessibility is the primary barrier. Grinberg's own analysis inadvertently validates RISC-V's strength: he derives requirements for cheap microcontrollers (low interrupt latency, small die area, good code density) and arrives at RV32EC—the exact core he criticizes.

Three current shipping chips demonstrate RISC-V's versatility: the ten-cent CH32V003 for simple embedded tasks, the high-performance CH32H417 with dual cores and advanced peripherals, and Baochip's VEX core with MMU supporting full operating systems. This diversity proves RISC-V successfully serves both ends of the spectrum, contradicting claims that a single ISA cannot accommodate both cost-constrained microcontrollers and high-performance applications.