A new version of the Project Oberon System has been migrated from Oberon 07 to the more common Oberon 90, using the OP2 compiler with a RISC-V (RV32) backend. The repository also includes a VM emulating Wirth’s original machine, built from a stripped‑down rv32emu backend and a custom hardware implementation. The memory map is reproduced 1:1, so Kernel, Display, and Input modules remain unchanged.

The original Oberon work, created by Niklaus Wirth and Jürg Gutknecht in the late 1980s, used the now‑obsolete NS32032. Wirth later designed the RISC‑5 processor, a single‑chip FPGA рішення, to keep the system simple. This migration to RISC-V preserves those design goals while leveraging widely available microcontrollers such as the ESP32 family from Espressif and development boards from Olimex.

The OP2 compiler, part of the ET H Oberon heritage, has been updated to generate code for RV32, avoiding the need to modify Wirth’s original OR compiler. The result is a compact, fully documented system that can run on modern hardware without an MMU.

Future work will port the system to the ESP32‑P4‑PC board, making the classic Oberon OS accessible to hobbyists and researchers alike.