Intel's AMX extension accelerates matrix multiplication for ML via tile registers and the TMUL accelerator on Sapphire Rapids and Granite Rapids-D CPUs. The x86 Ecosystem Advisory Group now specifies ACE, a second AMX accelerator.

Unlike configurable TMUL, ACE fixes tiles at 64x16 rows, drops complex numbers, adds FP8 support, and uses outer product instructions instead of inner products. This matches Arm's SME/SME2 approach, though Arm uses variable vector lengths (128–2048 bits) and ZA storage (256B–64KB) versus AMX's fixed 8KB tile registers.

Both handle quantized weights via software pre-processing. ACE leverages AVX-512's 512-bit vectors with VUNPACKB and VPERMB/VPERMI2B for flexible 2–7 bit conversion. SME2 adds a fixed 512-bit ZT0 register with LUTI2/LUTI4 instructions, limited to 2/4-bit formats. ACE's method offers broader data type support and potential for compression codebooks.